User Contributed MET/CAL PROCEDURE ============================================================================= INSTRUMENT: Sub PM 6304 (Performance) Part#1 IEEE / 6680 DATE: 01-Jun-95 AUTHOR: User Contributed REVISION: 1.0 ADJUSTMENT THRESHOLD: 95% NUMBER OF TESTS: 39 NUMBER OF LINES: 268 CONFIGURATION: Fluke 8842A CONFIGURATION: Philips PM 6680 ============================================================================= STEP FSC RANGE NOMINAL TOLERANCE MOD1 MOD2 3 4 CON 1.001 ASK+ D 1.002 ASK- R N P J F W 1.003 HEAD {4.4 Performance Verification} 1.004 DISP Connect the UUT to the IEEE port 1. 1.005 IEEE *IDN?[I$] 1.006 DISP Hi I am a: [MEM2] 1.007 RSLT =Software Version: [MEM2] 1.008 RSLT =RS232 interface installed 1.009 MATH MEM1=M[20] 1.010 JMPZ 1.012 1.011 RSLT =DC unit installed 1.012 MATH MEM1=M[19] 1.013 JMPZ 1.015 1.014 RSLT =Handler interface installed 1.015 HEAD {4.4.1 Test Voltage} 1.016 DISP Connect the UUT input to the 8840 input using the 1.016 DISP PM 6303 testcable. 1.017 IEEE *RST;TEST_SIG_AC;FRE 1E3[10] 1.018 RSLT =Normal Level 1.019 8842 10 1.000V 0.02U 1kH 2W 2.001 MATH MEM1=M[20] 2.002 JMPZ 3.001 2.003 IEEE TEST_SIG DC[10] 2.004 8842 10 1.000V 0.04U 2W 3.001 IEEE TEST_SIG AC;LEV LO;CON[10][10] 3.002 RSLT =Low Level 3.003 8842 100 50.00mV 2U 1kH 2W 4.001 MATH MEM1=M[20] 4.002 JMPZ 5.001 4.003 IEEE TEST_SIG DC[10] 4.004 8842 1000 300.0mV 12U 2W 5.001 IEEE TEST_SIG AC;LEV HI[10][10] 5.002 RSLT =High Level 5.003 8842 10 2.000V 0.04U 1kH 2W 6.001 MATH MEM1=M[20] 6.002 JMPZ 7.001 6.003 IEEE TEST_SIG DC[10] 6.004 8842 10 2.000V 0.08U 2W 7.001 HEAD {4.4.2 Test Signal Frequency} 7.002 DISP Disconnect the 8840. Connect the UUT input to the 6680 7.002 DISP Ch A input using the PM 6303 test cable and a dual 7.002 DISP bananna to BNC adapter. 7.003 IEEE TEST_SIG AC;FRE 100E3[10] 7.004 M680 ChA 7.005 6680 100.000kH 0.01% 3Vpp +A FA L 8.001 HEAD {4.4.3 Open-Circuit Trimming} 8.002 DISP Remove all connections. Connect Open Circuit test post 8.002 DISP adapter to the two left positions. 8.002 DISP 8.002 DISP The display should show BUSY, PASS, and about 8.002 DISP 0.0 pF finally. 8.003 IEEE *RST;[D999]FRE 100;TRIM;*OPC?[10][I] 8.004 EVAL Did the UUT pass the Open-Circuit Trim? 9.001 HEAD {4.4.4 Short-Circuit Trimming} 9.002 DISP Remove all connections. Connect Short Circuit test post 9.002 DISP adapter to the two left positions. 9.002 DISP 9.002 DISP The display should show BUSY, PASS, and about 9.002 DISP 0.000 ohm finally. 9.003 IEEE TRIM;*OPC?[10][I] 9.004 IEEE CON[10] 9.005 EVAL Did the UUT pass the Short-Circuit Trim? 10.001 HEAD {4.4.5 AC Measurements - 100 Hz Test Frequency} 10.002 DISP Remove all connections. Connect 4 Ohm Standard Resistor 10.002 DISP to the two left positions. 10.003 MATH MEM1=M[2] 10.004 IEEE LEV LO;CON[10][D999] 10.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 10.005 MEME 10.006 MEMC 1 ohm 1.2% 0.0000U LowLevel 11.001 MATH MEM1=M[2] 11.002 IEEE LEV NO[10][D999] 11.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 11.004 MEME 11.005 MEMC 1 ohm 1.1% 0.0000U NormalLevel 12.001 MATH MEM1=M[2] 12.002 IEEE LEV HI[10][D999] 12.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 12.004 MEME 12.005 MEMC 1 ohm 0.15% 0.0000U HighLevel 13.001 DISP Connect 500 Kohm Standard Resistor to the two left 13.001 DISP positions. 13.002 MATH MEM1=M[5] 13.003 IEEE LEV NO;CON[10][D999] 13.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 13.005 MEM/ 1000 13.006 MEME 13.007 MEMC 100 Kohm 1.2% 0.00U LowLevel 14.001 MATH MEM1=M[5] 14.002 IEEE LEV NO[10][D999] 14.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 14.004 MEM/ 1000 14.005 MEME 14.006 MEMC 100 Kohm 0.12% 0.00U NormalLevel 15.001 MATH MEM1=M[5] 15.002 IEEE LEV HI[10][D999] 15.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 15.004 MEM/ 1000 15.005 MEME 15.006 MEMC 100 Kohm 0.12% 0.00U HighLevel 16.001 HEAD {4.4.5 AC Measurements - 1 KHz Test Frequency} 16.002 DISP Remove all connections. Connect Open Circuit test post 16.002 DISP adapter to the two left positions. 16.003 IEEE *RST;[D999]FRE 1E3;TRIM;*OPC?[10][I] 16.004 DISP Remove all connections. Connect Short Circuit test post 16.004 DISP adapter to the two left positions. 16.005 IEEE TRIM;*OPC?[10][I] 16.006 IEEE CON[10] 16.007 DISP Connect 1 ohm Standard Resistor to the two left 16.007 DISP positions. 16.008 MATH MEM1=M[1] 16.009 IEEE LEV LO;CON[10][D999] 16.010 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 16.011 MEME 16.012 MEMC 1 ohm 1.5% 0.0000U LowLevel 17.001 MATH MEM1=M[1] 17.002 IEEE LEV NO[10][D999] 17.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 17.004 MEME 17.005 MEMC 1 ohm 0.52% 0.0000U NormalLevel 18.001 MATH MEM1=M[1] 18.002 IEEE LEV HI[10][D999] 18.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 18.004 MEME 18.005 MEMC 1 ohm 0.7% 0.0000U HighLevel 19.001 DISP Connect 4 ohm Standard Resistor to the two left 19.001 DISP positions. 19.002 MATH MEM1=M[2] 19.003 IEEE LEV LO;CON[10][D999] 19.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 19.005 MEME 19.006 MEMC 1 ohm 0.55% 0.0000U LowLevel 20.001 MATH MEM1=M[2] 20.002 IEEE LEV NO[10][D999] 20.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 20.004 MEME 20.005 MEMC 1 ohm 0.15% 0.0000U NormalLevel 21.001 MATH MEM1=M[2] 21.002 IEEE LEV HI[10][D999] 21.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 21.004 MEME 21.005 MEMC 1 ohm 0.15% 0.0000U HighLevel 22.001 DISP Connect 100 ohm Standard Resistor to the two left 22.001 DISP positions. 22.002 MATH MEM1=M[3] 22.003 IEEE LEV LO;CON[10][D999] 22.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 22.005 MEME 22.006 MEMC 100 ohm 0.55% 0.00U LowLevel 23.001 MATH MEM1=M[3] 23.002 IEEE LEV NO[10][D999] 23.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 23.004 MEME 23.005 MEMC 100 ohm 0.13% 0.00U NormalLevel 24.001 MATH MEM1=M[3] 24.002 IEEE LEV HI[10][D999] 24.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 24.004 MEME 24.005 MEMC 100 ohm 0.13% 0.00U HighLevel 25.001 DISP Connect 10 Kohm Standard Resistor to the two left 25.001 DISP positions. 25.002 MATH MEM1=M[4] 25.003 IEEE LEV LO;CON[10][D999] 25.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 25.005 MEM/ 1000 25.006 MEME 25.007 MEMC 10 Kohm 0.55% 0.000U LowLevel 26.001 MATH MEM1=M[4] 26.002 IEEE LEV NO[10][D999] 26.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 26.004 MEM/ 1000 26.005 MEMC 10 Kohm 0.12% 0.000U NormalLevel 27.001 MEME 27.002 MATH MEM1=M[4] 27.003 IEEE LEV HI[10][D999] 27.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 27.005 MEM/ 1000 27.006 MEME 27.007 MEMC 10 Kohm 0.12% 0.000U HighLevel 28.001 DISP Connect 500 Kohm Standard Resistor to the two left 28.001 DISP positions. 28.002 MATH MEM1=M[5] 28.003 IEEE LEV LO;CON[10][D999] 28.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 28.005 MEM/ 1000 28.006 MEME 28.007 MEMC 100 Kohm 0.55% 0.00U LowLevel 29.001 MATH MEM1=M[5] 29.002 IEEE LEV NO[10][D999] 29.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 29.004 MEM/ 1000 29.005 MEME 29.006 MEMC 100 Kohm 0.13% 0.00U NormalLevel 30.001 MATH MEM1=M[5] 30.002 IEEE LEV HI[10][D999] 30.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 30.004 MEM/ 1000 30.005 MEME 30.006 MEMC 100 Kohm 0.13% 0.00U HighLevel 31.001 DISP Connect 2 Mohm Standard Resistor to the two left 31.001 DISP positions. 31.002 MATH MEM1=M[6] 31.003 IEEE LEV LO;CON[10][D999] 31.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 31.005 MEM/ 1000000 31.006 MEME 31.007 MEMC 1 Mohm 1.55% 0.0000U LowLevel 32.001 MATH MEM1=M[6] 32.002 IEEE LEV NO[10][D999] 32.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 32.004 MEM/ 1000000 32.005 MEME 32.006 MEMC 1 Mohm 0.12% 0.0000U NormalLevel 33.001 MATH MEM1=M[6] 33.002 IEEE LEV HI[10][D999] 33.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 33.004 MEM/ 1000000 33.005 MEME 33.006 MEMC 1 Mohm 0.12% 0.0000U HighLevel 34.001 DISP Connect 100 Mohm Standard Resistor to the two left 34.001 DISP positions. 34.002 MATH MEM1=M[7] 34.003 IEEE LEV NO[10][D999] 34.004 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 34.005 MEM/ 1000000 34.006 MEME 34.007 MEMC 100 Mohm 5.5% 0.00U NormalLevel 35.001 MATH MEM1=M[7] 35.002 IEEE LEV HI[10][D999] 35.003 IEEE RESI?[10][I][D999];RESI?[10][I][D999];RESI?[10][I] 35.004 MEM/ 1000000 35.005 MEME 35.006 MEMC 100 Mohm 2.5% 0.00U HighLevel 36.001 DISP Connect 10 nF Standard Capacitor to the two left 36.001 DISP positions. 36.002 MATH MEM1=M[8] 36.003 IEEE LEV LO;CON[10] 36.004 IEEE CAP?[10][I][D999];CAP?[10][I][D999];CAP?[10][I] 36.005 MEM* 1000000000 36.006 MEME 36.007 MEMC 10 nF 0.7% 0.000U LowLevel 37.001 MATH MEM1=M[8] 37.002 IEEE LEV NO[10] 37.003 IEEE CAP?[10][I][D999];CAP?[10][I][D999];CAP?[10][I] 37.004 MEM* 1000000000 37.005 MEME 37.006 MEMC 10 nF 0.3% 0.000U NormalLevel 38.001 MATH MEM1=M[8] 38.002 IEEE LEV HI[10] 38.003 IEEE CAP?[10][I][D999];CAP?[10][I][D999];CAP?[10][I] 38.004 MEM* 1000000000 38.005 MEME 38.006 MEMC 10 nF 0.3% 0.000U HighLevel 39.001 CALL Sub PM 6304 (Performance) Part#2 IEEE 39.002 HEAD The END